Time Domain Architecture (TDA) US Patent 4,847,755.
TDA is a multi-disciplined technology covering a new operating system architecture, a new compiler architecture, and a new way of programming for engineers that need control of the hardware. TDA is better known as Multi-Core and Hyper-Threading Technology, the marketing term used by the industry, Intel calls the processor elements Cores. For any TDA to work well, a new instruction set architecture (ISA) had to be created that allowed the compilers to schedule instructions in parallel without conflict for resources. The instructions were then able to convey that temporal and logic information to the hardware.
But in my research I found that there wasn't enough work to keep the processor elements (PEs) busy all the time. So I invented multi-context for the operating system so that when a PE (core) was not busy the OS could electronically switch to a different waiting context. Traditional context-switching is expensive since it requires saving all of the state for the current application. That can mean hundred-of-thousands of instructions. So I invented three-dimensional register files so the context switch was now electronic. This added another dimension to the OS. So you can see that going from the traditional von Neumann single-core single-thread computer to a Multi-Core multi-threading computer is not a trivial change in the hardware architecture, the operating system, the compilers, or for the programmer.
In TDA the compiler does all of the static analysis and optimizations to guarantee no conflicts. One of the compiler optimizations I invented provided for multiple-cycle complex branches. The compiler assigns instruction firing times (IFT) to all of the instructions and calculates the number of instructions the branch could delay or actually advance the branch determination(s), and makes logical process number (LPN) assignments in an effort to keep all of the PEs busy.
The OS is responsible to make sure that when there is an empty time slot that an electronic context switch is executed. The concept is that simple, but the actual implementation and reduction to practice is more complex. The PEs in my patent are pipelined with four stages. These pipelines need to be considered when designing electronic switching. It gets worse when some of Intel's pipelines extended over twenty stages. Overall performance increases with multi-cores and overall throughput increases with multiple contexts.
The greatest everyday user will see the most improvement in throughput primarily because there is a minimal amount of truly parallel per instruction in ordinary use. The multi-context means that the OS can get out of your way and let you get more work done.